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Program of the workshop

The program of the Workshop is updated as information comes

SUNDAY June 27th 2010
before 19.30 Arrival and registration of participants
past 19.30 Welcome dinner


MONDAY June 28th 2010
9.00 - 10.30 Session I: Side Channel Attacks I

M. Nassar, Y. Souissi, S. Guilley and J. L. Danger:
The "Rank Correction" Technique to Improve Side-Channel Attacks

J. Di Battista, B. Rouzeyre, L. Torres, J. C. Courrege:
Side-Channel improvement by laser stimulation

P. Nguyen, H. Triqui:
Pinpointing the leakage of dual-rail logics in FPGAs

11.00 - 12.30 Session II: Cryptographic Architectures

F. Arnault, T. Berger, C. Lauradoux, M. Minier, B. Pousse:
New LFSRs and FCSRs representations for stream ciphers hardware and software design

J. Crenne, R. Tessier, P. Cotret, G. Gogniat, J. P. Diguet:
Securing External Shared Memory in Multi-FPGA Context

L. Gaspar, V. Fischer, F. Bernard, M. Drutarovsky:
Cryptographic processor with secured key management

12.45 - 14.00 Lunch
15.00 - 16.00 Invited talk

S. Chaumette:
The Relationship between Hardware Design and Software Level Security in Highly Dynamic Mobile ad hoc Networks

16.30 - 18.00 Session III: Side Channel Attacks II

G. Di Natale, M. L. Flottes, B. Rouzeyre, M. Valka:
Waveforms re-alignment to improve DPA attacks

H. Maghrebi, J. L. Danger and S. Guilley:
Leakage Squeezing Countermeasure Against High Order Attacks

W. Schindler, M. Kasper, M. Stottinger:
The Stochastic Approach in Power Analysis - An Efficient Attack and Useful Tool for Target-Oriented Design

past 19.30 Dinner


TUESDAY June 29th 2010
9.00 - 10.30 Session IV: Cryptographic Protocols

F. Devic, L. Torres, B. Badrignans:
Secure protocol implementation for remote bitstream update preventing replay attacks on FPGA

A. Idrissa, A. Aubert, T. Fournel, V. Fischer:
Secure Protocols for Serverless Remote Product Authentication

M. Agoyan, B. Robisson, P. Bazargan-Sabet, G. Phan, S. Le Henaff:
Smart On Smart: An innovative secured system architecture concept

11.00 - 12.30 Session V: Random Number Generation

M. Dichtl and B. Meyer:
Using Higher Harmonics of Ring Oscillators for Physical Random Number Generation on FPGAs

M. Drutarovsky and M. Varchola:
Analysis of Randomness Sources in Transition Effect Ring Oscillator based TRNG

J. Hlavac, M. Hadacek, R. Lorencz:
Generating true random bits on general-purpose microcontrollers

12.45 - 14.00 Lunch
15.00 - 16.30 Session VI: Random Number Generation & Benchmarking

D. Lubicz:
On the security of oscillator-based random number generators

K. Gaj, J. P. Kaps, V. Amirineni, M. Rogawski, E. Homsirikamol, B. Y. Brewster, J. Pham, and M. Varchola:
ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware using FPGAs

V. Fischer, F. Bernard, B. Valtchanov, and N. Bochard:
About the randomness in Ring Oscillator-based True Random Number Generators in FPGAs

17.00 - 18.30 Session VII: Hashing Functions

C. Lauradoux, M. Minier, T. Risset, W. Znaidi:
Why should we find new universal hash functions with good hardware implementation ?

M. Rogawski, E. Homsirikamol and K. Gaj:
SHA-3 Competition in Hardware - Methodology, Tools, and Results of Comparing Fourteen Round 2 SHA-3 Candidates using Reconfigurable Hardware

J. Francq et C. Thuillet:
High-Speed Implementation of the SHA-3 Candidate Shabal

past 19.30 Dinner-Cruise on the Seine


WEDNESDAY June 30th 2010
8.00 - 9.00 Breakfast
9.00 - 13.00 Visit of Montmartre Village
13.00 - 14.30 Lunch

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