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VHDL code for TRNG designs

Coherent Sampling Based TRNG Using PLLs

Architecture of the PLL-TRNG core

• lab_hc_pkg
• pll_trng
  • pll_trng_core
  • RO_core
    • buff_wrp (for Cyclone 5)
    • buff_wrp (for SmartFusion 2)
    • buff_wrp (for Spartan 6)
  • pll1_wrp (for Cyclone 5)
  • pll1_wrp (for SmartFusion 2)
  • pll1_wrp (for Spartan 6)
  • pll2_wrp (for Cyclone 5)
  • pll2_wrp (for SmartFusion 2)
  • pll2_wrp (for Spartan 6)
  • obuf_wrp (for Cyclone 5)
    • obuf_cyV (for Cyclone 5)
  • obuf_wrp (for SmartFusion 2)
  • obuf_wrp (for Spartan 6)