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VHDL code for TRNG designs

Self timed ring based TRNG

Architecture of the STR-TRNG core

• lab_hc_pkg
• STR_trng
  • str_trng_core
    • str_core
      • mcell_r_inv
        • mgate_r_inv
      • mcell_s_inv
        • mgate_s_inv
    • d_ff
    • XOR_tree
      • xr4
      • d_ff
  • RO_core
    • buff_wrp (for Cyclone 5)
    • buff_wrp (for SmartFusion 2)
    • buff_wrp (for Spartan 6)
  • obuf_wrp (for Cyclone 5)
    • obuf_cyV (for Cyclone 5)
  • obuf_wrp (for SmartFusion 2)
  • obuf_wrp (for Spartan 6)