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Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration
B. Gierlichs
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| We first summarize security issues that arise in the context of physical attacks, such as power and fault analysis, against implementations of cryptographic algorithms. Further, we compare some traditional countermeasures for hardware and software implementations.
In the second part of the talk we demonstrate how dynamic reconfiguration can realize a range of classical countermeasures for software implementations that were not easily portable to hardware so far. Further, we introduce a new class of countermeasures that provide increased resistance, in particular against fault attacks, by randomly relocating functional blocks on the chip area at run-time, or before every new execution of the implemented algorithm. Moreover, we show how fault detection can be provided on certain devices with negligible area-overhead. |
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