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A very low cost DPA countermeasures to secure hardware AES cipher
Lilian Bossuet, Najeh Kamoun, Adel Gazel
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To secure cryptography hardware implementation many works are focusing on side-channels attacks. For such attacks, several different countermeasures can be done at different abstraction levels abstraction. However, all published countermeasures lead to a significant area and power consumption overhead. With this work, we propose a novel countermeasure against DPA attack which also leads to relatively small implementation compared to existing countermeasures such as the most used: masking schemes.
Our idea is based in interfering the power trace with a signal which depends on the manipulated data and an interfering key. This approach removes the design power correlation with the useful key. Its efficiency is proved with a practical DPA attack realization on Actel Fusion FLASH FPGA and Xilinx Virtex 4 SRAM FPGA. With the proposed countermeasures, the full 128-bits AES implementation on Xilinx Virtex 4 has a smaller area overhead (12.78 times less) than the most used countermeasures. The area overhead with unsecure implementation is lower than 5%.
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