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New FPGA based TRNG Principle Using Transition Effect with Built-In Malfunction Detection
Michal Varchola, Milos Drutarovsky
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| We present and analyze a new method of randomness extraction using logic gates only. Random behavior was observed in a Modified Ring Oscillator - with selectable even or odd inverters as follows; first the oscillator uses odd number of inverting elements in order to raise oscillations. After a while number of inverting elements is switched to even. The oscillation does not stop immediately and excited pulse continues to travel around the ring. Length of this pulse is shortened by each loop, while the oscillation disappears completely. Number of loops completed differs in each new cycle, and thus represents a source of randomness. The entropy of this source seems to be higher in comparison to the entropy of standard ring oscillator composed of the same number of elements. Furthermore, one can easily detect whether the random bit was generated in sufficient way by simple transition counting and setting an optimal threshold region of their count. If the number of oscillation does not fit to the threshold region, generated bit will not be used in the resulting random bit sequence and an alarm could be issued. That leads to an alternative usage of such a circuit - it can be used for detecting a violation of operating conditions caused by possible attack. This method has disadvantage in terms of generating random bit-streams - dependence on operating conditions of the FPGA circuit. Slight change of the power supply voltage or temperature results in significant change of the number of oscillation and oscillator can even stop completely. It is possible to overcome this problem with ease by adding the second switching element to the chain (switching element behaves as inverter/buffer regarding to level of control signal). Thus we have a circuit that employs an even number of inverters regardless to level of the control signal and is stable because of a positive feedback. When a rising or falling edge appears in the control signal the stability of circuit is disturbed. This transition effect causes oscillations in the circuit that are dumped over the time as was discussed above. This enhancement decreases sensitivity on the operating conditions significantly. If we use a LSB of counter as a random bit, resulting random sequence does not satisfy FIPS-140 requirements completely and thus postprocessor should be used. Sampling frequency depends on the number of involved elements but it is possible go up to 5 MHz. Principle was evaluated in Xilinx Spartan 3E FPGA. |
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