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| Invited talks on application of reconfigurable logic devices in cryptography | |
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| M. McLoone: | High Speed SHACAL-2 Hardware Architecture |
| K. Gaj: | Cryptographic libraries for high-end reconfigurable computers |
| K. Gaj: | Implementation of the matrix step of the Number Field Sieve factorization algorithm in reconfigurable hardware |
| I. Toli: | Keyspace Redundancies of the HFE and Implications on Its Implementation |
| J. Pelzl, M. Simka: | Hardware-based Factorization of Integers with the Elliptic Curve Method: Part I |
| M. Simka, J. Pelzl: | Hardware-based Factorization of Integers with the Elliptic Curve Method: Part II |
| M. Renaudin: | Introduction to Asynchronous Logic |
| M. Renaudin: | Improving DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits |
| F. Bouesse: | Designing Resistant Asynchronous Circuits Against Malicious Fault Injection |
| F. Bouesse: | Prototyping Asynchronous Circuits on LUT-based FPGAs |
| L. Torres: | Current Masking Generation Technique: A Case Study |
| A. Razafindraibe, P. Maurine: | Asynchronous Techniques Against DPA Attack |
| S. Guilley: | CMOS structures and CAD Methods for the Design of DPA-proof ASICs |
| L. Torres, D. Mesquita: | Reconfigurable Architecture for Cryptography |
| M. Drutarovsky: | An Optimization of Scalable Montgomery Coprocessor Embedded in Reconfigurable Hardware |
| M. Drutarovsky: | Comments on the NIST Statistical Testing of a PLL-based TRNG Embedded in FPGA |
| V. Fischer: | On the Security of FPGA-based Architectures |
| S. Guilley: | Secured FPGAs |
Updated frequently ...