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Implementation and Evaluation of WDDL countermeasures in FPGAs
J.-L. Danger, S. Guilley, L. Sauvage, T. Graba, Y. Mathieu
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Unlike ASICs, in which custom and backend-level counter-measures can be
devised, FPGAs offer less possibilities for a designer to implement
counter-measures. We investigate ``wave dynamic differential logic'' (WDDL),
a logic-level
counter-measure based on leakage hiding thanks to balanced dual-rail logic.
First of all, we report a CAD methodology for achieving WDDL in FPGA. An
experimental security evaluation of the DES encryption algorithm in WDDL
shows that the usage of positive logic is mandatory to resist to
straightforward attacks.
Second, we discuss how to reduce the size overhead associated with WDDL. The
efficiency of some synthesizers is assessed. In the case of DES, we provide
with an original heuristic to obtain substitution boxes smaller than those
generated automatically with legacy ASIC synthesizers. Finally we study the
balanceness of the layout so as to obtain equal
propagation delays and power consumption on both rails. It is shown to which
extent the differential place-and-route constraints must be strict in FPGA
technology. |
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