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Prototyping STTL Robustness Against DPA and DEMA on FPGA: Proof of Concept
V. Lomne, R. Soares, T. Ordas, P. Maurine, L. Torres, M. Robert
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| Side channel attacks are known to be efficient techniques to retrieve secret data. Within this context, the scope
of this presentation is to prototype on FPGA the robustness against power analyses of a logic called Secure
Triple Track Logic. More precisely, this paper aims at demonstrating that the basic concepts on which leans this
logic are valid and may provide interesting design guidelines to obtain DPA resistant circuits and more robust
circuits against DEMA and CEMA. The results obtained highlight that a precise control of timings is mandatory to
obtain secure dual rail designs, and more precisely, DPA resistant circuits. |
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