| Invited talks on application of reconfigurable logic devices in cryptography |
| |
| B. Badrignans: |
Reconfigurable cryptographic processor on FPGA |
| F. Bernard: |
Time-Area Tradeoffs Improvement for Montgomery Modular Multiplication Implementation |
| J.-L. Beuchat: |
Arithmetic Operators for Pairing-Based Cryptography |
| L. Bossuet, G. Gogniat: |
How to Teach Hardware Security? |
| J. Bucek, R. Lorenz: |
Comparison of Different Implementations of Montgomery Modular Inverse in Hardware |
| G. Di Natale: |
Test and Security |
| V. Fischer: |
Implementation of True Random Number Generators in (Reconfigurable) Logic Devices |
| K. Gaj: |
An Optimized Hardware Architecture of Montgomery Multiplication Algorithm |
| K. Gaj: |
Emerging New Stream Ciphers vs. AES: Comparative Study of Hardware Performance |
| P. Hoogvorst: |
Random and Pseudo-Random Variable Generation |
| M. Hubner: |
Exploiting Dynamic and Partial Reconfiguration for Cryptographic Applications |
| P. Piasentin: |
New Actel FPGA Families for Low-Power Systems on Chip |
| S. Roy, R. Santoro: |
New Architectures for the Diffie-Hellman Key Exchange Based on Elliptic Curves |
| R. Santoro, O. Sentieys: |
Accelerating Statistical Tests for Real-Time Estimation of Randomness |
| M. Simka: |
Requirements on Reconfigurable Platform for DRM Implementations |
| R. Tessier: |
Distributed On-Chip Monitoring for Secure Embedded Systems |
| R. Vaslin: |
High Efficiency Protection Solution for Off-Chip Memory in Embedded Systems |
| E. Wanderley: |
A Code Compression Method with Encryption and Integrity Checking |
