| M. Agoyan, B. Robisson, P. Bazargan-Sabet, G. Phan, S. Le Henaff | Smart On Smart: An innovative secured system architecture concept |
|
| F. Arnault, T. Berger, C. Lauradoux, M. Minier, B. Pousse | New LFSRs and FCSRs representations for stream ciphers hardware and software design |
|
| S. Chaumette | The relationship between hardware design and software level security in highly dynamic mobile ad hoc networks |
|
| J. Crenne, R. Tessier, P. Cotret, G. Gogniat, J. P. Diguet | Securing External Shared Memory in Multi-FPGA Context |
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| F. Devic, L. Torres, B. Badrignans | Secure protocol implementation for remote bitstream update preventing replay attacks on FPGA |
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| J. Di Battista, B. Rouzeyre, L. Torres, J. C. Courrege | Side-Channel improvement by laser stimulation |
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| M. Dichtl and B. Meyer | Using Higher Harmonics of Ring Oscillators for Physical Random Number Generation on FPGAs |
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| G. Di Natale, M. L. Flottes, B. Rouzeyre, M. Valka | Waveforms re-alignment to improve DPA attacks |
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| M. Drutarovsky and M. Varchola | Analysis of Randomness Sources in Transition Effect Ring Oscillator based TRNG |
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| J. Francq et C. Thuillet | High-Speed Implementation of the SHA-3 Candidate Shabal |
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| K. Gaj, J. P. Kaps, V. Amirineni, M. Rogawski, E. Homsirikamol, B. Y. Brewster, J. Pham, and M. Varchola | ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware using FPGAs |
|
| L. Gaspar, V. Fischer | Cryptographic processor with secured key management |
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| J. Hlavac, M. Hadacek, R. Lorencz | Generating true random bits on general-purpose microcontrollers |
|
| A. Idrissa, A. Aubert, T. Fournel, V. Fischer | Secure Protocols for Serverless Remote Product Authentication |
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| C. Lauradoux, M. Minier, T. Risset, W. Znaidi | Why should we find new universal hash functions with good hardware implementation ? |
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| D. Lubicz | On the security of oscillator-based random number generators |
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| H. Maghrebi, J. L. Danger and S. Guilley | Leakage Squeezing Countermeasure Against High Order Attacks |
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| M. Nassar, Y. Souissi, S. Guilley and J. L. Danger | The "Rank Correction" Technique to Improve Side-Channel Attacks |
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| P. Nguyen, H. Triqui | Pinpointing the leakage of dual-rail logics in FPGAs |
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| M. Rogawski, E. Homsirikamol and K. Gaj | SHA-3 Competition in Hardware - Methodology, Tools, and Results of Comparing Fourteen Round 2 SHA-3 Candidates using Reconfigurable Hardware |
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| W. Schindler, M. Kasper, M. Stottinger | The Stochastic Approach in Power Analysis - An Efficient Attack and Useful Tool for Target-Oriented Design |
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