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| Registration |
| Participants |
| Presentations |
| Workshop place |
| Photos |
| Contact |
| Club members |
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The program of the Workshop is updated as information comes
| SUNDAY June 17th 2018 | |
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| From 17.30 | Arrival and registration of participants in Guidel-Plages |
| 19.00 - 20.30 | Dinner |
| MONDAY June 18th 2018 | |
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| 7.00 - 8.30 | Breakfast |
| 9.00 - 10.00 | Session I: New encryption schemes Cyrielle Feron, Vianney Lapotre, Loïc Lagadec, ENSTA Brest, Lab-STICC Lorient, France Parameter Exploration for Homomorphic Encryption Schemes Analysis William Diehl, Abubakr Abdulgadir, Farnoud Farahmand, Kris Gaj, and Jens-Peter Kaps, George Mason University, USA Evaluation of DPA Protected Implementations of CAESAR Finalists ACORN and Ascon and other Candidates |
| 10.30 - 12.00 | Session II: Post quantum cryptography Kris Gaj, Ahmed Ferozpuri, Viet Dang, Duc Nguyen, Farnoud Farahmand, Jens-Peter Kaps, George Mason University, USA Post-Quantum Cryptography in Reconfigurable Hardware: Challenges, Opportunities, and State-of-the-Art Tania Richmond, Benoit Gerard, Annelie Heuser and Axel Legay, Inria, IRISA, Rennes, France Side-channel Information Leakage of the Syndrome Computation in Code-Based Cryptography Felipe Valencia, Francesco Regazzoni, ALaRI - USI, Lugano, Switzerland Fault Attack Resistance of Post Quantum Algorithms |
| 12.30 - 13.30 | Lunch |
| 14.30 - 16.00 | Session III: Attacks Eloi de Chérisey, Sylvain Guilley, Olivier Rioul, Télécom ParisTech, France Confusing Information Audrey Lucas, CNRS - IRISA - INRIA, Rennes, France A Simulator for Evaluating the Leakage in Arithmetic Circuits Alexandre Menu, Jean-Luc Danger, Jean-Max Dutertre, Elias Kharbouche, Olivier Potin, and Jean-Baptiste Rigaud, Mines St-Etienne, CEA-Tech, Institut Mines-Telecom, Gardanne, France Targeting several unpipelined instructions with a single electromagnetic pulse on 8-bit microcontroller |
| 16.30 - 17.30 | Session IV: True Random Number Generators Maciej Skorski, Elie Noumon Allini, IST Austria, Lab. Hubert Curien, St-Etienne, France Evaluating Min-Entropy of Random Bits by Markov Chains Viktor Fischer, Oto Petura, Ugo Mureddu, Nathalie Bochard, Marek Laban, Lab. Hubert Curien, St-Etienne, France HECTOR TRNG design approach and its demonstration |
| 19.00 - 20.30 | Dinner |
| TUESDAY June 19th 2018 | |
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| 7.00 - 8.30 | Breakfast |
| 9.00 - 10.00 | Session V: Physical Unclonable Functions Bertrand Cambou, Northern Arizona University, Flagstaff, Arizona, USA Addressable PUF Generators for Database-free Password Management System Alexander Schaub, J-Luc Danger, Sylvain Guilley, Olivier Rioul, Télécom ParisTech, France Reliability and Entropy of Delay PUFs: A Theoretical Analysis |
| 10.30 - 12.00 | Session VI: Countermeasures against physical attacks Brice Colombier, Pierre-Alain Moëllic, CEA, Gardanne, France Security evaluation of countermeasures against physical attacks inserted at compilation time Stanislav Jeřábek, Martin Novotný, Jan Schmidt, Czech Technical University, Prague Dummy rounds as a DPA countermeasure Maria Mushtaq, Ayaz Akram, Muhammad Khurram Bhatti, Vianney Lapotre, Guy Gogniat, Lab-STICC Lorient, France Cache-Based Side-Channel Intrusion Detection using Hardware Performance Counters |
| 12.30 - 13.30 | Lunch |
| 14.30 - 16.00 | Session VII: Implementation of cryptographic architectures Nele Mentens, Edoardo Charbon, Francesco Regazzoni, KU Leuven, Belgium, EPFL, ALaRI, Switzerland Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow Cuauhtemoc Mancillas-López, Mridul Nandi, Lab. Hubert Curien, St-Etienne, Indian Statistical Institute, India Spongy-Gift: A New Lightweight Message Authentication Code Michal Andrzejczak, Military University of Technology Warsaw, Poland An Improved Architecture of a Hardware Accelerator for Factoring Integers with Elliptic Curve Method |
| 16.30 - 17.30 | Session VIII: Mixed PUF/TRNG circuits S. Buchovecká, R. Lórencz, J. Buček, F. Kodýtek, Czech Technical University, Prague Secure authentication and communication for embedded systems using a PUF/TRNG combined circuit J-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Kazuo Sakiyama, Sylvain Guilley, Télécom ParisTech, France Mixed PUF-TRNG Circuit using Body Biasing in FD-SOI |
| 19.00 - 20.30 | Dinner |
| WEDNESDAY June 20th 2018 | |
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| 7.00 - 8.30 | Breakfast |
| 10.00 | Social event Visit to the "citée de la voile, Eric Tabarly", museum on sailing and offshore race boats (boats, equipments, history, games, etc): https://www.citevoile-tabarly.com/en/ |
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