File structure

The file structure for hardware simulation and synthesis projects depends on the design tool used. For Altera Quartus II and Xilinx ISE tools we recommend to place the design files into three directories (this strategy is applied in all examples from Section "Design examples":

• Shared: this directory contains all files that are shared by the simulation and synthesis tools (VHDL files, hex files, etc.)
• Simul: this directory contains the ModelSim project, all simulation-specific VHDL files and two directories containing input and output scripts (scripts_in and scripts_out, respectively)
• Synth: this directory contains the reconfigurable hardware project and all synthesis-specific VHDL files

In the context of the Microsemi Libero design tools, the shared files are placed in the hdl directory (user defined files) and in the smartgen or component directories, the simulation files and directories are placed in the simulation directory and the synthesis files are placed in the synthesis directory. Note that the structure of the project and thus the names of the project directories are imposed by the Libero tool.

VHDL synthesis and device configuration

The synthesis project file should include all the VHDL files from the shared and synth directories. If some hex files are used (e.g. for embedded memory initialization), they should be placed in the synth directory. The project creation depends on the vendor and the design tool. The first example in Section "Design examples" includes eight projects for eight available families and modules:

• Altera Cyclone III
• Altera Cyclone V
• Altera Arria II
• Xilinx Spartan 3
• Xilinx Spartan 6
• Xilinx Virtex 5
• Microsemi Fusion
• Microsemi SmartFusion 2

Other application projects can be created accordingly. All FPGA modules contain small configuration connectors. Connectors on Altera and Xilinx FPGA modules contain interface for both device SRAM configuration and for configuration memory programming. Small adapter cards are available for connecting standard configuration cables such as Altera USB Blaster, Xilinx Platform Cable USB II and Microsemi FlashPro (or compatible) with FPGA modules. Altera and Xilinx adapter cards contain both JTAG interface for device configuration and proprietary interface for configuration memory programming. For the three new Evariste III modules, the JTAG_IN connector of the V1.2 motherboard can also be used to configure the FPGA.

Once the design of the application hardware is finished, the device configuration bitstream can be programmed into the configuration memory and the application is directly available once the card is plugged into the USB connector via standard USB cable. Note that before programming or configuring the card, the Evariste III motherboard must by powered from the USB bus or from some external power supply (by default, the card is powered from the USB bus). If the card is powered from the USB bus (the most frequent case), two USB cables are needed: one for powering the card and communicate with the host PC and the other for configuring the device or programming the configuration memory.