Difference between revisions of "Reference designs"
(Created page with "The next examples present two typical cases of using the Evariste III system. They include both simulation and synthesis projects and script files for testbenches and hardware...") |
(→Hardware design) |
||
| (2 intermediate revisions by one user not shown) | |||
| Line 5: | Line 5: | ||
==Hardware design== | ==Hardware design== | ||
| − | The hardware that should be implemented inside FPGA is described in | + | The hardware that should be implemented inside FPGA is described in 8 vhdl files placed in three folders as described in section ''file structure'' (''shared'', ''simul'' and ''synth'' folders). The structure of user files in project folders is presented in the next table (in alphabetical order): |
[[Image:09_Synthtransfer2usb.jpg]] | [[Image:09_Synthtransfer2usb.jpg]] | ||
| Line 12: | Line 12: | ||
Implementation of the ''transfer2usb project'' in different FPGA families does not need specification of any constraints. In order to obtain maximum speed, we recommend to set the ''clk_ctrl'' clock as close to 48 MHz as possible (maximum frequency allowed by Cypress). | Implementation of the ''transfer2usb project'' in different FPGA families does not need specification of any constraints. In order to obtain maximum speed, we recommend to set the ''clk_ctrl'' clock as close to 48 MHz as possible (maximum frequency allowed by Cypress). | ||
| + | |||
''Attention: the second clock generated by the PLL (or DLL in Spartan 3), i.e. usbifclk_out, must be advanced by 6 ns!'' | ''Attention: the second clock generated by the PLL (or DLL in Spartan 3), i.e. usbifclk_out, must be advanced by 6 ns!'' | ||
| Line 18: | Line 19: | ||
[[Image:09_Simultransfer2usb.jpg]] | [[Image:09_Simultransfer2usb.jpg]] | ||
| + | |||
The next figure shows input script file | The next figure shows input script file | ||
[[Image:09_Ex1_scriptin.jpg]] | [[Image:09_Ex1_scriptin.jpg]] | ||
| + | |||
The next figure shows output log file contents (as a response to the input script file) | The next figure shows output log file contents (as a response to the input script file) | ||
[[Image:09_Ex1_logout.jpg]] | [[Image:09_Ex1_logout.jpg]] | ||
Latest revision as of 12:16, 16 September 2015
The next examples present two typical cases of using the Evariste III system. They include both simulation and synthesis projects and script files for testbenches and hardware testing. The first project has height different versions – one version for each available FPGA device (module). The second project is built only for Altera Cyclone III device, but it can be adapted very easily to any of available devices (only PLL configuration and device pinout need to be changed).
High speed data transfer from the FPGA module via USB
This project demonstrates the way how high speed one directional data transfers can be made. It also shows what data rate can be obtained in full-speed hardware tests. It implements a simple bi-directional counter accessible from the USB bus.
Hardware design
The hardware that should be implemented inside FPGA is described in 8 vhdl files placed in three folders as described in section file structure (shared, simul and synth folders). The structure of user files in project folders is presented in the next table (in alphabetical order):
The application has two modes (set-up with the mode bits in the control register, bits ctrl2appl(2 .. 0) defined in file transfer2usb.vhd): in mode MODE_TST0 (mode N°3), a 128-bit counter is incremented, in MODE_TST1 (mode N°7) it is decremented. The counter is implemented in the applic_wrp.vhd file. Mode names and values are defined in the lab_hc_pkg.vhd file. The same values must be used in the software (script) calling the hardware.
Implementation of the transfer2usb project in different FPGA families does not need specification of any constraints. In order to obtain maximum speed, we recommend to set the clk_ctrl clock as close to 48 MHz as possible (maximum frequency allowed by Cypress).
Attention: the second clock generated by the PLL (or DLL in Spartan 3), i.e. usbifclk_out, must be advanced by 6 ns!
VHDL simulation using scripts
The ModelSim project is placed in the simul directory. After launching the ModelSim software, the user should first change the directory (File -> Change Directory...). Then he should write in the Transcript window: do tb.do in order to launch compilation and simulation. The simulator will open the bus_script_in.txt text file with script, it will read the commands and data and stimulate DUT. Generated waveforms will be displayed in the Waveform window and the response of the DUT will be written to the log file. The following table shows the structure of user files in simulation project folders.
The next figure shows input script file
The next figure shows output log file contents (as a response to the input script file)
