Difference between revisions of "Introduction"
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The devices of the last family represent an embedded SoC based on an ARM processor. | The devices of the last family represent an embedded SoC based on an ARM processor. | ||
| − | Besides the necessary hardware, the Evariste II/III system consist of a set of open source hardware design tools and an open source control and data acquisition software. The reconfigurable hardware design is made of four main IP (intellectual property) functions (USB controller interface, packet manager, application controller and application itself) and a testbench file for simulations | + | Besides the necessary hardware, the Evariste II/III system consist of a set of open source hardware design tools and an open source control and data acquisition software. The reconfigurable hardware design is made of four main IP (intellectual property) functions (USB controller interface, packet manager, application controller and application itself) and a testbench file for simulations. |
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Revision as of 09:13, 15 September 2015
The system Evariste III is aimed at development and evaluation of cryptographic functions and primitives in reconfigurable hardware. It is an evolution of the Evariste II system. It consists of a set of hardware, software and design tools making the development and evaluation of cryptographic functions easier. All the tools are open source and their reliable function was approved in many projects.
The hardware part of the system is composed of a module that contains an FPGA device. The module is plugged into a motherboard that contains power supply and communication elements. The first version of the system (Evariste II) includes five modules, each containing one of selected FPGA devices:
- Altera Cyclone III (EP3C25)
- Altera Arria II (EP2AGX45)
- Xilinx Spartan 3 (XC3S700AN)
- Xilinx Virtex 5 (XC5VLX30T)
- Actel Fusion (M7AFS600)
Besides FPGA device, some modules contain a 4MB SRAM memory with a 32-bit data access. All the modules have identical pin-out and can be plugged into the motherboard containing the Cypress EZ USB controller device thanks to a 56 pins dip connector. In order to reduce the noise in the context of random number generation or side channel attacks, all the modules and motherboards use only linear voltage regulators as FPGA power supplies. The hardware can be accessed from the PC via USB bus using an open source signed GNU driver compatible with Windows XP and Windows 7 – 10.
The Evariste III system includes some improvements. The new motherboard (V1.2) contains ZIF (zero insertion force) connectors to easily plug and unplug modules in a safe way. It also includes a JTAG chain that enables to configure several FPGAs through the same JTAG bus (this is very helpful in PUF characterization that needs numerous data acquisitions to be performed in different operating conditions). Eight extra pins have been added to the module connector to dispatch these JTAG signals. All old modules are still compatible with the new motherboard, letting 8 pins free, but the new modules are not compatible anymore with the old, V1.1, motherboard.
Three types of application modules have been designed for this new modular system. Each module is built around different FPGA family:
- Xilinx Spartan 6 (XC6SLX16)
- Altera Cyclone V (5CEBA4F17C8N)
- Microsemi SmartFusion2 (M2S025-FG484)
The devices of the last family represent an embedded SoC based on an ARM processor. Besides the necessary hardware, the Evariste II/III system consist of a set of open source hardware design tools and an open source control and data acquisition software. The reconfigurable hardware design is made of four main IP (intellectual property) functions (USB controller interface, packet manager, application controller and application itself) and a testbench file for simulations.
