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| Workshop place |
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| Contact |
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The program of the Workshop is updated as information comes
| SUNDAY June 23th 2019 | |
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| From 17.30 | Arrival and registration of participants in Průhonice |
| 19.00 - 20.30 | Welcome dinner: buffet |
| MONDAY June 24th 2019 | |
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| 7.00 - 8.30 | Breakfast |
| 9.00 - 10.30 | Session I: Lightweight crypto / IoT Cedric Marchand, Ecole Centrale de Lyon Internet of things security: review from communication to sensor Julien Francq, Airbus Defence & Space - CyberSecurity Design Exploration of the NIST LWC Competition Lilliput-AE Etienne Tehrani, Telecom ParisTech Acceleration of Lightweight Block Ciphers on Microprocessors |
| 11.00 - 12.30 | Session II: Masking and other countermeasures Vojtech Miskovsky, Czech Technical University in Prague Area-efficient fault-tolerant architectures exploiting masking scheme randomness Wei Cheng, Telecom ParisTech Optimal Codes for Inner Product Masking Tania Richmond, Inria - IRISA, Rennes Security aspects at the compilation level |
| 12.30 - 14.30 | Lunch |
| 14.30 - 16.00 | Session III: Microcontroller security Jan Riha, Czech Technical University in Prague Implementation and Effectiveness Evaluation of the VeraGreg Scheme on a Low-Cost Microcontroller Alexander Schaub, Telecom ParisTech STAnalyzer: A simple static analysis tool for detecting cache-timing leakages Petr Socha, Czech Technical University in Prague Toolkit for side-channel analysis: SICAK |
| 16.30 - 18.00 | Session IV: RNG security Marco Bucci, Infineon Technologies AG, Austria Offline and online testability of Random Number Generators Markus Dichtl, Germany How (not) to end up with dependent random bits Maciej Skorski, Dell, Austria Minimax Study of Bias Correctors |
| 19.00 - 20.30 | Dinner |
| TUESDAY June 25th 2019 | |
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| 7.00 - 8.30 | Breakfast |
| 9.00 - 10.30 | Session V: Deep learning and other attacks Francis Olivier, Thales-DIS (formerly Gemalto) Deep Learning versus Template Attacks: experimental comparison Damien Robissout, LabHC St-Etienne Improved Deep-Learning Side-Channel Attacks using Normalization layers Martin Jurecek, Czech Technical University in Prague Cryptanalysis of the A5/1 Using Power Analysis |
| 11.00 - 12.30 | Session VI: Hardware implementations Milos Grujic, imec-COSIC, KU Leuven, Belgium A Multimode Ring Oscillator based TRNG for FPGAs Bertrand Cambou, Northern Arizona University, USA Replacing error correction by key fragmentation and search engines To generate error-free cryptographic keys from PUFs Michal Andrzejczak, Military University of Technology in Warsaw, Poland Lattice sieving acceleration in FPGAs |
| 12.30 - 14.30 | Lunch |
| 14.30 - 16.00 | Session VII: Security challenges Kris Gaj, George Mason University, USA Toward Efficient and Fair Software/Hardware Codesign and Benchmarking of Candidates in Round 2 of the NIST PQC Standardization Process G. Richard Newell, Microchip Technology (FPGA Business Unit), USA Survey of Notable Security-Enhancing Activities in the RISC-V Universe Francesco Regazzoni, ALaRI - USI, Lugano Security Challenges in Cyber-Physical Systems |
| 16.30 - 18.00 | Session VIII: Physical attacks Ugo Mureddu, STMicroelectronics France Transient Effect Ring Oscillators Leak Too Brice Colombier, LabHC St-Etienne Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller Jan Belohoubek, Czech Technical University in Prague Modulated CMOS Static Power is Data Dependendent and Observable |
| 19.00 - 20.30 | Dinner |
| WEDNESDAY June 26th 2019 | |
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| 7.00 - 8.30 | Breakfast |
| 10.00 - 12.00 | Social event National Technical Museum |
| 12.00 - 14.00 | Lunch in Prague: Restaurant Holesovicka SEDMA |
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