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Proposed talks

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Authors, titles and abstracts (updated frequently)

Michal Andrzejczak, Military University of Technology in Warsaw, PolandLattice sieving acceleration in FPGAs
Jan Belohoubek, Czech Technical University in PragueModulated CMOS Static Power is Data Dependendent and Observable
Marco Bucci, Infineon Technologies AG, AustriaOffline and online testability of Random Number Generators
Bertrand Cambou, Northern Arizona University, USAReplacing error correction by key fragmentation and search engines To generate error-free cryptographic keys from PUFs
Wei Cheng, Telecom ParisTechOptimal Codes for Inner Product Masking
Brice Colombier, LabHC St-EtienneLaser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller
Markus Dichtl, GermanyHow (not) to end up with dependent random bits
Julien Francq, Airbus Defence & Space - CyberSecurityDesign Exploration of the NIST LWC Competition Lilliput-AE
Kris Gaj, George Mason University, USAToward Efficient and Fair Software/Hardware Codesign and Benchmarking of Candidates in Round 2 of the NIST PQC Standardization Process
Milos Grujic, imec-COSIC, KU Leuven, BelgiumA Multimode Ring Oscillator based TRNG for FPGAs
Martin Jurecek, Czech Technical University in PragueSPA and DPA attack on the A5/1 Stream Cipher
Cedric Marchand, Ecole Centrale de LyonInternet of things security: review from communication to sensor
Vojtech Miskovsky, Czech Technical University in PragueArea-efficient fault-tolerant architectures exploiting masking scheme randomness
Ugo Mureddu, STMicroelectronics FranceTransient Effect Ring Oscillators Leak Too
G. Richard Newell, Microchip Technology (FPGA Business Unit), USASurvey of Notable Security-Enhancing Activities in the RISC-V Universe
Francis Olivier, Thales-DIS (formerly Gemalto)Deep Learning versus Template Attacks: experimental comparison
Francesco Regazzoni, ALaRI - USI, LuganoSecurity Challenges in Cyber-Physical Systems
Tania Richmond, Inria - IRISA, RennesSecurity aspects at the compilation level
Jan Riha, Czech Technical University in PragueImplementation and Effectiveness Evaluation of the VeraGreg Scheme on a Low-Cost Microcontroller
Damien Robissout, LabHC St-EtienneImproved Deep-Learning Side-Channel Attacks using Normalization layers
Alexander Schaub, Telecom ParisTechSTAnalyzer: A simple static analysis tool for detecting cache-timing leakages
Maciej Skorski, Dell, AustriaMinimax Study of Bias Correctors
Petr Socha, Czech Technical University in PragueToolkit for side-channel analysis: SICAK
Etienne Tehrani, Telecom ParisTechAcceleration of Lightweight Block Ciphers on Microprocessors

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