| Michal Andrzejczak, Military University of Technology in Warsaw, Poland | Lattice sieving acceleration in FPGAs |
| Jan Belohoubek, Czech Technical University in Prague | Modulated CMOS Static Power is Data Dependendent and Observable |
| Marco Bucci, Infineon Technologies AG, Austria | Offline and online testability of Random Number Generators |
| Bertrand Cambou, Northern Arizona University, USA | Replacing error correction by key fragmentation and search engines To generate error-free cryptographic keys from PUFs |
| Wei Cheng, Telecom ParisTech | Optimal Codes for Inner Product Masking |
| Brice Colombier, LabHC St-Etienne | Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller |
| Markus Dichtl, Germany | How (not) to end up with dependent random bits |
| Julien Francq, Airbus Defence & Space - CyberSecurity | Design Exploration of the NIST LWC Competition Lilliput-AE |
| Kris Gaj, George Mason University, USA | Toward Efficient and Fair Software/Hardware Codesign and Benchmarking of Candidates in Round 2 of the NIST PQC Standardization Process |
| Milos Grujic, imec-COSIC, KU Leuven, Belgium | A Multimode Ring Oscillator based TRNG for FPGAs |
| Martin Jurecek, Czech Technical University in Prague | SPA and DPA attack on the A5/1 Stream Cipher |
| Cedric Marchand, Ecole Centrale de Lyon | Internet of things security: review from communication to sensor |
| Vojtech Miskovsky, Czech Technical University in Prague | Area-efficient fault-tolerant architectures exploiting masking scheme randomness |
| Ugo Mureddu, STMicroelectronics France | Transient Effect Ring Oscillators Leak Too |
| G. Richard Newell, Microchip Technology (FPGA Business Unit), USA | Survey of Notable Security-Enhancing Activities in the RISC-V Universe |
| Francis Olivier, Thales-DIS (formerly Gemalto) | Deep Learning versus Template Attacks: experimental comparison |
| Francesco Regazzoni, ALaRI - USI, Lugano | Security Challenges in Cyber-Physical Systems |
| Tania Richmond, Inria - IRISA, Rennes | Security aspects at the compilation level |
| Jan Riha, Czech Technical University in Prague | Implementation and Effectiveness Evaluation of the VeraGreg Scheme on a Low-Cost Microcontroller |
| Damien Robissout, LabHC St-Etienne | Improved Deep-Learning Side-Channel Attacks using Normalization layers |
| Alexander Schaub, Telecom ParisTech | STAnalyzer: A simple static analysis tool for detecting cache-timing leakages |
| Maciej Skorski, Dell, Austria | Minimax Study of Bias Correctors |
| Petr Socha, Czech Technical University in Prague | Toolkit for side-channel analysis: SICAK |
| Etienne Tehrani, Telecom ParisTech | Acceleration of Lightweight Block Ciphers on Microprocessors |
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