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The program of the Workshop is updated as information comes
SUNDAY May 29th 2022 | |
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18.30 | Departure of the last shuttle from la Tour Fondue to Porquerolles |
19.00 - 20.00 | Welcome cocktail |
20.00 | Dinner |
MONDAY May 30th 2022 | |
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7.15 - 8.45 | Breakfast |
9.00 - 10.30 | Session I: Physical and Side Channel Attacks 1 Mathieu Dumont, CEA-Leti / Mines Saint-Etienne, France Laser Fault Injection Against Embedded Neural Network Model Tomas Rabas, Czech Technical University in Prague SPA on NTRU software implementation Carlos Lara-Nino, LabHC St-Etienne, Univ Lyon, France DVFS covert-channels in Zynq Ultrascale+ SoC-FPGAs |
11.00 - 12.30 | Session II: Sources of Randomness in Random Number Generation Markus Dichtl, Germany On Jitter in Very Long Ring Oscillators Arturo Mollinedo Garay, STMicroelectronics / LabHC St-Etienne, France An evaluation procedure for comparing clock jitter measurement methods Richard Newell, Microchip Technology, USA The new RISC-V Entropy Source Instruction Set Architecture (ISA) Standard |
12.30 - 14.30 | Lunch |
14.30 - 15.30 | Session III: Post-quantum Cryptography Implementations Brice Colombier, TIMA, Univ Grenoble Alpes, France Physical Security of Code-based Cryptosystems based on the Syndrome Decoding Problem Markku-Juhani O. Saarinen, PQShield Ltd, Oxford, UK Side-Channel Leakage Tests for Post-Quantum Crypto Modules |
15.30 - 16.30 | Session IV: Attack Detection and Countermeasures Mateus Simoes, STMicroelectronics / LabHC St-Etienne, France Asynchronous S-Boxes Designing Clockless First-Order Masked Functions Roukoz Nabhan, EMSE/CEA, Gardanne, France Securing The IoT Against Fault Injection Attacks Using Digital Sensors |
17.00 - 18.00 | Session V: Secure Implementations of Cryptographic Applications Mohamed El-Bouazzati, Lab-STICC, Univ Bretagne Sud, France Towards Low-Power and Low Data-Rate Software-Defined Radio Baseband with RISC-V Processor for Flexibility and Security Ana I. Gomez, Universidad Rey Juan Carlos, Madrid, Spain A Case for the use of PUFs in Indoor Localization Systems |
19.15 - 20.30 | Dinner |
TUESDAY May 31st 2022 | |
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7.15 - 8.45 | Breakfast |
9.00 - 10.30 | Session VI: Hardware Implementations of Cryptography Primitives Loic France, LIRMM, Univ Montpellier, France Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations Louis Noyez, EMSE/CEA, Gardanne, France Scalable FPGA Hardware Models for Modular Multiplication Using AMNS Representation Cedric Marchand, Ecole Centrale de Lyon, France In-Memory implementation of SBoxes using Ferroelectric transistors |
11.00 - 12.30 | Session VII: Hardware Implementations of NIST Lightweight Cryptography Candidates Nathan Roussel, EMSE/CEA, Gardanne, France Hardware implementation of Ascon authenticated cipher based on CMOS/STT-MRAM Subhadeep Banik, Universita della Svizzera Italiana, Lugano, Switzerland A Small GIFT-COFB: Lightweight Bit-Serial Architectures Pierre-Antoine Tissot, LabHC St-Etienne, Univ Lyon, France Implementation challenges of Photon-Beetle, a NIST Standardization Finalist |
12.30 - 14.30 | Lunch |
14.30 - 16.30 | Session VIII: Physical and Side Channel Attacks 2 Julien Beguinot, Telecom ParisTech Unprofiled Expectation-Maximization Attack Khurram Bhatti, Lahore, Pakistan IE-Cache: Counteracting Eviction-Based Cache Side-Channel Attacks Through Indirect Eviction. Vincent Grosso, LabHC St-Etienne, Univ Lyon, France ASCA: Comparing Horizontal Side-Channel Attacks Yi Liu, Telecom ParisTech Evaluation of Side-Channel Attacks Using Alpha-Information |
19.15 - 20.30 | Dinner |
WEDNESDAY June 1st 2022 | |
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7.15 - 9.30 | Breakfast |
10.00 - 12.00 | Social event: Visit of the Villa Carmignac A space dedicated to contemporary art in a preserved green setting |
12.00 - 14.00 | Lunch at the restaurant "l'orangeraie", in Porquerolles |
14.30 - 15.00 | Shuttle to join la Tour Fondue on the mainland |