| Subhadeep Banik, Universita della Svizzera Italiana, Lugano, Switzerland | A Small GIFT-COFB: Lightweight Bit-Serial Architectures |
| Julien Beguinot, Telecom ParisTech | Unprofiled Expectation-Maximization Attack |
| Khurram Bhatti, Lahore, Pakistan | IE-Cache: Counteracting Eviction-Based Cache Side-Channel Attacks Through Indirect Eviction. |
| Brice Colombier, TIMA, Univ Grenoble Alpes, France | Physical Security of Code-based Cryptosystems based on the Syndrome Decoding Problem |
| Markus Dichtl, Germany | On Jitter in Very Long Ring Oscillators |
| Mathieu Dumont, CEA LETI, France | Laser Fault Injection Against Embedded Neural Network Model |
| Mohamed El-Bouazzati, Lab-STICC, Univ Bretagne Sud, France | Towards Low-Power and Low Data-Rate Software-Defined Radio Baseband with RISC-V Processor for Flexibility and Security |
| Loic France, LIRMM, Univ Montpellier, France | Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations |
| Ana I. Gomez, Universidad Rey Juan Carlos, Madrid, Spain | A Case for the use of PUFs in Indoor Localization Systems |
| Vincent Grosso, LabHC St-Etienne, Univ Lyon, France | ASCA: Comparing Horizontal Side-Channel Attacks |
| Carlos Lara-Nino, LabHC St-Etienne, Univ Lyon, France | DVFS covert-channels in Zynq Ultrascale+ SoC-FPGAs |
| Yi Liu, Telecom ParisTech | Evaluation of Side-Channel Attacks Using Alpha-Information |
| Cedric Marchand, Ecole Centrale de Lyon, France | In-Memory implementation of SBoxes using Ferroelectric transistors |
| Arturo Mollinedo Garay, STMicroelectronics France | An evaluation procedure for comparing clock jitter measurement methods |
| Roukoz Nabhan, EMSE/CEA, Gardanne, France | Securing The IoT Against Fault Injection Attacks Using Digital Sensors |
| Richard Newell, FPGA Business Unit, Microchip Technology, USA | The new RISC-V Entropy Source Instruction Set Architecture (ISA) Standard |
| Louis Noyez, EMSE/CEA, Gardanne, France | Scalable FPGA Hardware Models for Modular Multiplication Using AMNS Representation |
| Tomas Rabas, Czech Technical University in Prague | SPA on NTRU software implementation |
| Nathan Roussel, EMSE/CEA, Gardanne, France | Hardware implementation of Ascon authenticated cipher based on CMOS/STT-MRAM |
| Markku-Juhani O. Saarinen, PQShield Ltd, Oxford, UK | Side-Channel Leakage Tests for Post-Quantum Crypto Modules |
| Mateus Simoes, STMicroelectronics France | Asynchronous S-Boxes Designing Clockless First-Order Masked Functions |
| Pierre-Antoine Tissot, LabHC St-Etienne, Univ Lyon, France | Implementation challenges of Photon-Beetle, a NIST Standardization Finalist |
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PORQUEROLLES 2022
