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Proposed talks

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Authors, titles and abstracts

Subhadeep Banik, Universita della Svizzera Italiana, Lugano, SwitzerlandA Small GIFT-COFB: Lightweight Bit-Serial Architectures
Julien Beguinot, Telecom ParisTechUnprofiled Expectation-Maximization Attack
Khurram Bhatti, Lahore, PakistanIE-Cache: Counteracting Eviction-Based Cache Side-Channel Attacks Through Indirect Eviction.
Brice Colombier, TIMA, Univ Grenoble Alpes, FrancePhysical Security of Code-based Cryptosystems based on the Syndrome Decoding Problem
Markus Dichtl, GermanyOn Jitter in Very Long Ring Oscillators
Mathieu Dumont, CEA LETI, FranceLaser Fault Injection Against Embedded Neural Network Model
Mohamed El-Bouazzati, Lab-STICC, Univ Bretagne Sud, FranceTowards Low-Power and Low Data-Rate Software-Defined Radio Baseband with RISC-V Processor for Flexibility and Security
Loic France, LIRMM, Univ Montpellier, FranceReducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations
Ana I. Gomez, Universidad Rey Juan Carlos, Madrid, SpainA Case for the use of PUFs in Indoor Localization Systems
Vincent Grosso, LabHC St-Etienne, Univ Lyon, FranceASCA: Comparing Horizontal Side-Channel Attacks
Carlos Lara-Nino, LabHC St-Etienne, Univ Lyon, FranceDVFS covert-channels in Zynq Ultrascale+ SoC-FPGAs
Yi Liu, Telecom ParisTechEvaluation of Side-Channel Attacks Using Alpha-Information
Cedric Marchand, Ecole Centrale de Lyon, FranceIn-Memory implementation of SBoxes using Ferroelectric transistors
Arturo Mollinedo Garay, STMicroelectronics FranceAn evaluation procedure for comparing clock jitter measurement methods
Roukoz Nabhan, EMSE/CEA, Gardanne, FranceSecuring The IoT Against Fault Injection Attacks Using Digital Sensors
Richard Newell, FPGA Business Unit, Microchip Technology, USAThe new RISC-V Entropy Source Instruction Set Architecture (ISA) Standard
Louis Noyez, EMSE/CEA, Gardanne, FranceScalable FPGA Hardware Models for Modular Multiplication Using AMNS Representation
Tomas Rabas, Czech Technical University in PragueSPA on NTRU software implementation
Nathan Roussel, EMSE/CEA, Gardanne, FranceHardware implementation of Ascon authenticated cipher based on CMOS/STT-MRAM
Markku-Juhani O. Saarinen, PQShield Ltd, Oxford, UKSide-Channel Leakage Tests for Post-Quantum Crypto Modules
Mateus Simoes, STMicroelectronics FranceAsynchronous S-Boxes Designing Clockless First-Order Masked Functions
Pierre-Antoine Tissot, LabHC St-Etienne, Univ Lyon, FranceImplementation challenges of Photon-Beetle, a NIST Standardization Finalist

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