| Markus Dichtl, Siemens Corporate Technology, Germany | ALESSIO, a Research Project on Updatable Security Components of Persistent Industrial Embedded Systems |
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| Markus Dichtl, Siemens Corporate Technology, Germany | Fibonacci Ring Oscillators as True Random Number Generators - A Security Risk |
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| Brice Colombier, Lilian Bossuet, David Hély, Lab. Hubert Curien, St-Etienne | Centrality Indicators For Efficient And Scalable Logic Masking |
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| Gabriel Gallin, Arnaud Tisserand, CNRS - IRISA - LabSTICC, France | Hardware Architectures for HECC |
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| Richard Newell, Microsemi Corp., USA | Improving Trust in the FPGA Supply Chain using Blockchain and Keyless-Signature Technology |
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| Vojtech Miskovsky, Czech Technical University, Prague | Influence of Fault Tolerant Design Techniques on Resistance against Differential Power Analysis |
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| Audrey Lucas, Arnaud Tisserand, CNRS - IRISA - LabSTICC, France | ECC Protections against both Observation and Pertubation Attacks |
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| J-Luc Danger, O. Rioul, S.Guilley, A. Schaub, Télécom ParisTech | Formalism to assess the Loop-PUF entropy and reliability |
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| W. Adi, A. Mars, S. Mulhem, Technical University of Braunschweig, Germany | Clone-resistant structures in Microsemi SoC units |
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| K. Karray, J-L Danger, S. Guilley, A. El Aabid, Télécom ParisTech | Attack tree construction: an application to the connected vehicle |
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| Malik Umar Sharif, Ahmed Ferozpuri and Kris Gaj, George Mason University, USA | Lessons Learned from High-Speed Implementation and Benchmarking of Two Post-Quantum Public-Key Cryptosystems |
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| Tania Richmond, Laboratoire IMATH, Toulon, France | Low-complexity DPA Countermeasure for Resource-Constrained Embedded McEliece Implementation |
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| Elie Noumon Allini, Florent Bernard, Viktor Fischer, LaHC St-Etienne, France | An illustration of a new certiffication approach for TRNGs |
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| Tomas Fabsic, Ondrej Gallo, Viliam Hromada, Slovak University of Technology, Bratislava, Slovakia | Demonstration of the Acoustic Cryptanalysis |
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| Brice Colombier et al., Lab. Hubert Curien, St-Etienne | Complete activation scheme for IP design protection |
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| Jan Belohoubek, Czech Technical University, Prague | The Design-Time Side-Channel Information Leakage Estimation |
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| Francesco Regazzoni, Felipe Valencia, ALaRI - USI, Lugano, Switzerland | Power Analysis Resistance of Lattice-based Cryptosystems |
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| Marcel Kleja, Marek Laban, Viktor Fischer, Technical University of Kosice, Micronic, Slovakia | Secure Portable USB Data Storage |
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