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Program of the workshop

The program of the Workshop is updated as information comes

SUNDAY June 18th 2017
From 17.30 Arrival and registration of participants in Smolenice
19.30 Dinner

MONDAY June 19th 2017
8.00 - 9.00 Breakfast
9.00 - 10.30 Session I: Design protection

Audrey Lucas, Arnaud Tisserand, CNRS - IRISA - LabSTICC, France
ECC Protections against both Observation and Pertubation Attacks

Brice Colombier, Lilian Bossuet, David Hely, Lab. Hubert Curien, St-Etienne
Centrality Indicators For Efficient And Scalable Logic Masking

Tania Richmond, Laboratoire IMATH, Toulon, France
Low-complexity DPA Countermeasure for Resource-Constrained Embedded McEliece Implementation

11.00 - 12.00 Session II: Side channel attacks

Vojtech Miskovsky, Czech Technical University, Prague
Influence of Fault Tolerant Design Techniques on Resistance against Differential Power Analysis

Jan Belohoubek, Czech Technical University, Prague
The Design-Time Side-Channel Information Leakage Estimation

12.00 - 14.30 Lunch
14.30 - 15.30 Session III: Physical Unclonable Functions

J-Luc Danger, O. Rioul, S.Guilley, A. Schaub, Telecom ParisTech
Formalism to assess the Loop-PUF entropy and reliability

W. Adi, A. Mars, S. Mulhem, Technical University of Braunschweig, Germany
Clone-resistant structures in Microsemi SoC units

16.00 - 17.00 Session IV: Implementation of cryptographic architectures with demonstration

Marcel Kleja, Marek Laban, Viktor Fischer, Technical University of Kosice, Micronic, Slovakia
Secure Portable USB Data Storage

Brice Colombier et al., Lab. Hubert Curien, St-Etienne
Complete activation scheme for IP design protection

19.30 Dinner

TUESDAY June 20th 2017
8.00 - 9.00 Breakfast
9.00 - 10.30 Session V: Random Number Generation

Markus Dichtl, Siemens Corporate Technology, Germany
Fibonacci Ring Oscillators as True Random Number Generators - A Security Risk

Markus Dichtl, Siemens Corporate Technology, Germany
ALESSIO, a Research Project on Updatable Security Components of Persistent Industrial Embedded Systems

Viktor Fischer, LaHC St-Etienne, France
Design and evaluation of a physical random number generator (guideline for certification)

Elie Noumon Allini, Florent Bernard, Viktor Fischer, LaHC St-Etienne, France
An illustration of a new certification approach for TRNGs

11.00 - 12.00 Session VI: Attack schemes

K. Karray, J-L Danger, S. Guilley, A. El Aabid, Telecom ParisTech
Attack tree construction: an application to the connected vehicle

Tomas Fabsic, Ondrej Gallo, Viliam Hromada, Slovak University of Technology, Bratislava, Slovakia
Demonstration of the Acoustic Cryptanalysis

12.00 - 14.30 Lunch
14.30 - 15.30 Session VII: Post Quantum Cryptosystems

Francesco Regazzoni, Felipe Valencia, ALaRI - USI, Lugano, Switzerland
Power Analysis Resistance of Lattice-based Cryptosystems

Malik Umar Sharif, Ahmed Ferozpuri and Kris Gaj, George Mason University, USA
Lessons Learned from High-Speed Implementation and Benchmarking of Two Post-Quantum Public-Key Cryptosystems

16.00 - 17.00 Session VIII: Implementation of cryptographic architectures

Gabriel Gallin, Arnaud Tisserand, CNRS - IRISA - LabSTICC, France
Hardware Architectures for HECC

Richard Newell, Microsemi Corp., USA
Improving Trust in the FPGA Supply Chain using Blockchain and Keyless-Signature Technology

19.30 Dinner

WEDNESDAY June 21st 2017
8.00 - 9.00 Breakfast
9.30 - 12.00 Social event:
Guided tour of Trnava City and wine tasting
12.00 - 14.00 Lunch in Trnava city

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